The schematic of the constant-\(g_m\) bias circuit is shown in Fig. 1. It consists of two cross-coupled current mirrors, where one of the source contacts, e.g. of an NMOS transistor, is degenerated by a source resistor. This results in a unique operating point of the circuit other than zero current, which defines the pass current in the two branches.
To illustrate the operation, we use the simple quadratic MOS-model, where the gate voltage \(V_{GS}\) can be expressed as
$$\begin{equation}
V_{GS} = \sqrt{\frac{2 I_{DS}}{\beta}}+V_{TH}
\end{equation}$$
where \(I_{DS}\) is the drain current, \(\beta\) is a gain factor holding technology constants and geometry dimensions, i.e. \(\beta = K_{n/p} \frac{W}{L}\), and \(V_{TH}\) is the transistor threshold voltage. Both NMOS transistors \(NM_0\) and \(NM_1\) have the same gate voltage, which yields in the condition
$$\begin{equation}
V_{GS0} = V_{GS1} + I_{REF} R_{S}
\end{equation}$$
where \(I_{REF}\) is the reference current of interest, equal to the drain current \(I_{DS}\) of the transistor \(NM_1\), and \(R_S\) is the source resistance of the transistor \(NM_1\). Rearrangement of expression yields for reference current in
$$\begin{equation}
I_{REF} = \frac{2}{R_S^2 \beta_0} \lbrace 1 – \frac{1}{\sqrt{K}} \rbrace ^2\end{equation}$$
where \(K\) is the geometry ratio of the transistors \(NM_0\) and \(NM_1\) and \(\beta_0\) is the gain of transistor \(NM_0\). Setting (K = 4) results in a transconductance \(g_{m0}\) of transistor \(NM_0\) of
$$\begin{equation}
g_{m0} = \sqrt{2 \beta_0 I_{REF}} = \frac{1}{R_S}\: (K=4)
\end{equation}$$
Consequently, all derived transconductances of transistor \(NM_0\) are defined by the source resistance \(R_S\), which will be constant for moderate temperature dependence of \(R_S\).
The above relationship is given for the case of strong inversion, but we can do a similar calculation for weak inversion or sub-threshold operation. The gate source voltage can be expressed in sub-threshold operation as
$$\begin{equation}
V_{GS} = n \frac{kT}{q} ln \frac{I_D}{\beta} = n V_{th} ln \frac{I_D}{\beta}
\end{equation}$$
with \(kT/q\) as the thermal voltage, and \(\beta = \frac{W}{L} \mu_n C_{ox} (n-1) V_{th}^2 e^{-V_{TH}/(nV_{th})}\). Rearranging, the reference current will yield in
$$\begin{equation}
I_{REF} = \frac{n V_{th}}{R_S} ln K
\end{equation}$$
and again for the transconductance \(g_{m0}\) of transistor \(NM_0\) one derives a value of
$$\begin{equation}
g_{m0} = \frac{I_{REF}}{n V_{th}} = \frac{ln K}{R_S} = \frac{1}{R_S}\: (ln K=1)
\end{equation}$$
This is the same expression as for strong inversion if a different weighting factor \(k\) is considered.
The corresponding settings of \(\textit{SizingTool}\) 3 for for transistor \(NM_0\) and for transistor \(NM_1\) are given in Fig. 2 and Fig. 3. Assuming a given transconductance \(g_m\) of \(100 \mu S\) at a drain current of \(10 \mu A\) and a saturation voltage of around \(150 mV\), we adjusted the dimensions accordingly to \(W_{DR}\) = \(10 \mu m\) and \(L_{DR}\) = \(2 \mu m\) (see Fig. 2). Note that transistor \(NM_0\) is in diode-connected mode, as suggested by the schematic. These settings are considered for typical situations, which is a reasonable assumption as we will be realising a constant-\(g_m\) bias that is valid for all process corners anyway. As for transistor \(NM_1\), its dimensions are given by the dimensions of transistor \(NM_0\) and the ratio K, hence \(W_{DR}\) = \(40 \mu m\) and \(L_{DR}\) = \(2 \mu m\), with \(K = 4\). The drain current \(I_{DS1} = I_{REF}\) is also given as \(10 \mu A\). We then adjust the source-bulk voltage until the gate-bulk voltage of transistor \(NM_1\) is the same as the gate-source voltage of transistor \(NM_0\), which is approximately \(85 mV\). With \(I_{DS1} = I_{REF} = 10 \mu A\), we calculate for the source-resistor \(R_S\) a value of \(85 k\Omega\).
In Fig. 4 the simulated drain currents are given for all process corners and junction temperatures as a function of supply current (assuming \(PM_0\) and \(PM_1\) with \(W_{DR}\) = \(30 \mu m\) um and \(L_{DR}\) = \(2 \mu m\)) as predicted by a commercial simulator tool. The power supply rejection is reasonable, but the process corner and temperature dependence is not. However, we are not so much interested in the reference current, but rather in the transconductance \(g_m\) and its behaviour over process corners and temperature, which is given in Fig. 5. There, a \(g_m\)-accuracy of \(+/- 5\%\) is achieved over all variations (temperature coefficient and resistance variation of \(R_S\) not taken into account).
Once the drain currents for a constant-\(g_m\) biasing block are known, we can use the information when designing any other transistor with derived source current. However, there its drain current has to be readjusted each time the process corner is changed to reflect for constant-\(g_m\) biasing, which is tedious, and is addressed by the current weighing option.
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