The Miller-OTA amplifier is widely used in CMOS technology and is sufficient for many applications. If your gain requirements are within ±70 to 80 dB, your load is reasonable (preferably only capacitive), and you require only a single-ended output, the Miller-OTA is a good choice. Its simplicity, straightforward biasing, and wide output range make it an attractive option.
In this article, we will briefly discuss the design synthesis of the amplifier, review the design procedure for operational amplifiers based on the constant current density method, and provide step-by-step instructions on how to size each transistor in the design.
Often, designers tend to reuse amplifiers from other projects because they hesitate to redesign an amplifier from scratch. The goal of this article is to demonstrate that, even if the design is more complex than the one presented here, using the systematic approach provided can quickly fulfill the design requirements. This method allows you to design an amplifier tailored to your specific needs whenever required.
The schematic of the amplifier is shown in Fig. 1. While we will not delve into the theory of pole-splitting, which is covered extensively in many textbooks. However, we will provide a simplified circuit analysis. The schematic in Fig. 1 can be redrawn as a mixed block diagram, as shown in Fig. 2 and Fig. 3. Note that Fig. 3 includes an additional nulling resistor not present in Fig. 1. For simplicity, we have made the assignments \(g_{m1}\) = \(g_{m11}\) = \(g_{m12}\)and \(g_{m2}\) = \(g_{m21}\).
A quick circuit analysis reveals the dominant pole \(\omega_{p1}\), the non-dominant pole \(\omega_{p2}\), and the zero due to the nulling resistor \(\omega_{z2}\). In the absence of the nulling resistor, we tend to neglect the zero \(\omega_{z2}\) since it typically appears at very high frequencies. However, if the nulling resistor is present, we have an additional design option by placing the zero \(\omega_{z2}\) close to the non-dominant pole to cancel it out. The required conditions can be easily derived by setting \(\omega_{p2}\) equal to \(\omega_{z2}\).
$$\begin{equation}
\omega_{p1} = \frac{g_{m11}}{A_0 C_{M}}
\end{equation}$$
$$\begin{equation}
\omega _{p2} = \frac{g_{m21}}{C_{L}}
\end{equation}$$
$$\begin{equation}
\omega _{z2} = \frac{g_{m21}}{C_{M} (1-g_{21} R_{M} )}
\end{equation}$$
For readers interested in exploring the subject further and deriving all the poles and zeros occurring in the design, we provide the equivalent circuit shown in Fig. 4.
Starting from this schematic, we have identified the following poles and zeros, though not claiming completeness.
$$\begin{equation}
A_{0} = \frac{g_{m11} g_{m21}} {g_{o1} g_{o2}}
\end{equation}$$
$$\begin{equation}
\omega_{z1} = \frac{2 g_{m13} g_{o0}}{2 C_{gs13}}
\end{equation}$$
$$\begin{equation}
\omega_{z2} = \frac{g_{m21}}{(C_M+C_{gd14}) (1-g-{m21} R_M)}
\end{equation}$$
$$\begin{equation}
\omega_{p2} \approx \frac{C_{2go1}+(C_M+C_{gd21})g_{m21}+C_{1go2}}
{ C_{1} C_{2}-(C_M+C_{gd21})^2}
\end{equation}$$
$$\begin{equation}
g_{o0} = g_{ds11}+g_{ds13}
\end{equation}$$
$$\begin{equation}
g_{01} = g_{ds12}+g_{ds14}
\end{equation}$$
$$\begin{equation}
g_{02} = g_{ds21}+g_{ds22}
\end{equation}$$
$$\begin{equation}
C_{1} = C_{M}+ C_{gs21}+ C_{gd12}+ C_{gd14}+ C_{gd21}
\end{equation}$$
$$\begin{equation}
C_{2} = C_{M}+ C_{L}+ C_{gs21}+ C_{gd21}+ C_{gd22}
\end{equation}$$
$$\begin{equation}
C_{3} = 2C_{gs13}+ C_{gd11}+ C_{gd13}
\end{equation}$$
$$\begin{equation}
\omega_{p1} \approx \frac{g_{01}+g_{go2}} {C{2} g_{o1} (C_M+C_{gd21}) g_{m21}+C_{1} g_{o2}}
\end{equation}$$
$$\begin{equation}
\omega_{p3} = \frac{g_{m13}+g_{o1}}{ C_{3}}
\end{equation}$$
$$\begin{equation}
\omega_{z3} = -\frac{g_{m12}}{ C_{gd12}}
\end{equation}$$
$$\begin{equation}
\omega_{z1} = \frac{2g_{m13}+g_{o0}}{2 C_{gs13}}
\end{equation}$$
For those who want to optimize their amplifier with respect to noise, we will provide the relevant equations as follows
$$\begin{equation}
V_{neq}{2}(f) = 2V_{n1}^2(f)+2V_{n2}^2(f)(\frac{g_{m2}}{g_{m1}})^2
\end{equation}$$
$$\begin{equation}
V_{neq}{2}(f) = 8kT \frac{2}{3} \frac{1}{g_{m1}}(1+\frac{g_{m2}}{g_{m1}})
\end{equation}$$
Only the thermal noise contribution is given; however, flicker noise behaves similarly. To minimize noise, optimize or adjust \(g_{m1}\)and \(g_{m2}\)accordingly.
The following design process for the amplifier will adhere to a standard procedure, which we will summarize in the list below.
Design Procedure, e.g. for OPAMPS (Current Density \(I_{DS}/W\) Based)
- Specifications: \(f_{3dB}\), \(H_1\), \(H_2\), \(V_{DD}\), \(V_{out}\) (swing), \(C_{load}\), error \(\epsilon\), \(V_{nRMS}\)
- Estimate secondary specifications: \(A_0\), \(\epsilon_{DC}\), \(\epsilon_{settling}\), \(f_u\), \(f_p\), …, \(V_{n,th}\), \(V_{n,1/f}\), \(f_k\), \(S_L\), …
- Choose topology based on \(A_0\), output swing, speed requirements, and do circuit analysis
- Define constant-\(g_m\) biasing block and note PT currents
- Get rough idea of relevant \(g_{m}\)’s w/ associated currents
- Define \(v_{dsat}\) and \(\) values based on specifications and secondary specifications (set \(v_{gs}\) to \(v_{ds}\)
- Adjust \(v_{dsat}\) for each MOST with \(L\) and \(I_{DS}/W\) with SizingTool (choose different PT’s, and currents)
- Adjust \(g_{m}\)’s according to \(f_{3dB} \), \(f_{u}\), \(f_{p}\), \(V_{n,th}\), \(V_{n,1/f}\) with SizingTool
- Confirm if all specifications are met with SizingTool, readjust and re-spin design procedure
- Verify with Spice simulator (AC, TR, NZ) and eventually optimize with SizingTool
- Optimize and review with SizingTool and annotated schematic
(PT: process corners, temperature corners)
The following design procedure is outlined for an amplifier design. However, this approach is not exclusive to amplifiers and can be applied to other circuits from a conceptual standpoint.
We begin the design process by gathering all relevant specifications, referred to as primary specifications. These primary specifications describe the desired behavior of the amplifier or circuit as a whole, without providing explicit details about the performance of individual design blocks within the circuit. For example, in the case of an amplifier, primary specifications might include the overall settling error, without specifying what this implies for the amplifier’s gain, bandwidth, or stability.
Next, we derive secondary specifications, which are more design-focused. These may include the required open-loop gain to achieve a specified minimum amplification error, or explicit bandwidth, poles, and zeros necessary to ensure stability. Secondary specifications are essential for assigning specific behaviors to individual circuit blocks, which is crucial for the subsequent sizing of the devices.
Next, we select a topology that we believe will meet the secondary specifications. This decision often relies on experience to make reasonable choices. However, if the chosen topology does not satisfy the specifications or proves to be overly complex, we may revisit this step and opt for a different topology, and start over again from this point.
An important aspect of selecting the topology is conducting a thorough circuit analysis. This helps determine whether the topology is likely to be successful and allows us to relate secondary block specifications to specific circuit devices. For example, it helps identify the required transconductance \(g_m\) and drain-source conductance \(g_{ds}\) needed to achieve the desired gains.
Primary Specifications
| Property | Value | Property | Value |
| \(V_{DD}\) | 3.3 V | \(\omega_{3db}\) | 2\(\pi\) 1.0 MHz |
| \(I_{DD}\) | <50 \(\mu\)A | \(V_{nRMS}\) | 250 \(\mu\)V |
| \(V_{OUT}\) | 0.5 … 2.8 V | \(\epsilon_{s}\) | 250 \(\mu\)V |
| \(C_{LOAD}\) | 10 pF | \(\epsilon_{DC}\) | 500 \(\mu\)V |
| \(H_{1}\)-\(H_{2}\) | 1.0 – 1.0 V | \(S_{L}\) | \(V_{OUT} \omega_{3dB}\) ¼ V/s |
| \(T_{junc}\) | -45/27/125 \(^\circ\)C | \(f_{k}\) | < 100kHz |
Secondary Specifications
| Property | Value | Property | Value |
| \(A_{0}\) | >66 dB | \(C_{M}\) | 3 pF |
| \(f_{u}\) | 1.0 MHz | \(g_{m11}\) | 20 \(\mu\)S |
| \(f_{p}\) | 3 … 4 \(f_u\) | \(g_{m21}\) | 250 \(\mu\)V |
The primary purpose of transistors is amplification, which involves the transconductance \(g_m\) and drain-source conductance \(g_{ds}\). Refer to the post on the constant current density method. Define the constant-\(g_m\) biasing block and note the PT currents. Obtain a rough idea of the relevant \(g_m\) values with their associated currents w/ SizingTool. As the next step, define \(V_{DSAT}\)and other values based on the specifications and secondary specifications (set \(V_{GS}\)to \(V_{DS}\)). As a rule of thumb, choose \(V_{DSAT}\) such that you can set the subsequent \(V_{DS}\) at least 200 mV higher without compromising any headroom. Adjust \(V_{DSAT}\) for each MOST with \(L\) and \(I_{DS}/W\) with SizingTool (choose different PT’s, and currents according the results of the constant-\(g_m\) biasing block).
Estimation of \(V_{dsat}\) and \(V_{DS}\)
| Device | Comment on \(V_{DSAT}\) |
| – | \(V_{DSAT}\) = \(V_{DS}\) – 0.2 V |
| \(M_{11}\)/\( M_{12}\) | Small (noise), or large (high SL) |
| \(M_{13}\)/\( M_{14}\) | Large (minimize input referred noise |
| \(M_{15}\) | For desired input swing (small) |
| \(M_{21}\) | For desired output swing (small, but high \(g_{DS}\)) |
| \(M_{22}\) | For desired output swing (small, but high \(g_{DS}\)) |
Once \(V_{DSAT}\), \(L\), and \(I_{DS}/W\)are known, adjust \(g_{m}\)’s according to \(f_{3dB} \), \(f_{u}\), \(f_{p}\), \(V_{n,th}\), \(V_{n,1/f}\) using the SizingTool. Increase \(I_{DS}\) while keeping \(I_{DS}/W\) constant, which impacts \(g_{m}\) while \(g_{ds}\) remains unchanged.
Adjustment \(V_{DSAT}\) and \(g_{m}\)’s According Specifications
| Device | \(V_{DSAT}\) [V] | \(L\) [\(\mu\)m] | \(I_{DS}/W\) [\(\mu A/\mu m\)] |
| \(M_{11}\)/\( M_{12}\) | 0.30 | 5.0 | 1.25/2.0 |
| \(M_{13}\)/\( M_{14}\) | 0.30 | 5.0 | 2.00/1.0 |
| \(M_{21}\) | 0.15 | 2.0 | 1.00/1.0 |
| Device | Type | \(W\)/\(L\) [-] | \(I_{DS}\) [\(\mu\)A] | \(g_{m}\) [\(\mu\)s] | \(g_{DS}\) [ns] |
| \(M_{11}\)/\( M_{12}\) | P | 8.00/5.0 | 5.0 | 20 | 250 |
| \(M_{13}\)/\( M_{14}\) | N | 2.50/5.0 | 5.0 | 20 | 320 |
| \(M_{21}\) | N | 25.0/2.0 | 25.0 | 250 | 700 |
| \(M_{22}\) | P | 75.0/2.0 | 25.0 | – | 630 |
| \(M_{15}\) | P | 30.0/2.0 | 10.0 | – | – |
Finally, confirm that all specifications are met using the SizingTool. If necessary, readjust and iterate the design procedure. Verify the design with a SPICE simulator (AC, transient, noise analysis) and optimize using the SizingTool. Review and refine the design with the SizingTool and an annotated schematic. Below in Fig. 8, the schematic for amplifier verification is shown (including the test-bench mentioned in a dedicated post). In Fig. 9, the simulation results predicted with a commercial simulator are displayed. Please note that these results are based on an initial attempt, without any optimization, and all specifications are met across process corners (PVT). The design procedure for the given example, from specification to verified schematic, took approximately one hour.
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